CD4073 Triple 3-input AND Gate

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CD4073 belongs to the 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD4073 has Triple 3-input AND Gate

CD4073 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.

CD4073 Features

  • Medium-Speed Operation – tPLH
    • tPHL 60 ns (typ.) at VDD 10 V
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin {full package-temperature range)
    • 1Vat VDD 5V
    • 2Vat VpDD 10 V
    • 2.5 V at VpD 15 V
  • Standardized, symmetrical output characteristics
  • 5-V.10-V, and 15-V parametric ratings

CD4073 Specifications

Absolute Maximum Ratings

  • DC Supply Voltage Range, (VDD): -0.5V to +20V (Voltage Referenced to VSS Terminals)
  • Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
  • DC Input Current, Any One Input: ±10mA
  • Operating Temperature Range: -55oC to +125oC Package Types D, F, K, H
  • Storage Temperature Range (TSTG): -65oC to +150oC
  • Lead Temperature (During Soldering): +265oC
    • At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum

CD4073 Pinout Diagram

CD4073 Pin Description

Pin NoPin NameDescription
1AInput 1 Of AND Gate 1
2B Input 2 Of AND Gate 1
3D Input 1 Of AND Gate 2
4E Input 2 Of AND Gate 2
5F Input 3 Of AND Gate 2
6K=D.E.FOutput Of AND Gate 2
7VSSSupply Voltage
8C Input 3 Of AND Gate 1
9J=A.B.C Output Of AND Gate 1
10L=G.H.I Output Of AND Gate 3
11I Input 1 Of AND Gate 3
12H Input 2 Of AND Gate 3
13G Input 3 Of AND Gate 3
14VDDDrain Voltage

CD4073 Circuit

Applications

  • Data transmission control in digital electronics

CD4073 Alternative Equivalent

CD4081, CD4082

Download CD4073 Triple 3-input AND Gate Datasheet from the link given below.